FIG. 1 shows an integrated semiconductor memory device 100 with a memory cell array 10, a control circuit 20 and an address register 30. The memory cell array 10 includes sense amplifiers SA which are in each case connected to a bit line pair BLP which includes a true bit line BLT and a complement bit line BLC. Within the memory cell array, memory cells SZ are arranged in the manner of a matrix along word lines WL and bit lines BLT and BLC of a bit line pair.
In the case of a DRAM (dynamic random access memory) semiconductor memory, a memory cell includes a selection transistor AT and a storage capacitor SC. To read information into memory cells SZ, for example for reading out information from the memory cell SZ, the selection transistor AT is controlled to conduct by a corresponding potential on the connected word line WL so that the storage capacitor SC is connected with low impedance to the bit line connected to the memory cell. For the evaluation of a cell signal, a sense amplifier SA is located at the end of one bit line pair. During the reading-out of a memory cell, an increase or a decrease in potential, the so-called potential swing, is produced on the bit line connected with low impedance to the storage capacitor. This swing is amplified by the sense amplifier connected to the bit line so that a data item D with a logical High or Low level is generated at a data terminal DQ.
To select a memory cell in the memory cell array of matrix-like structure, an address signal is applied to an address terminal A30 of the address register 30. The signal includes an address X and an address Y. Via the address X, a memory row (word line) can be selected and via the address Y, a column (bit line/bit line pair) can be selected. As a result, the memory cell arranged at the point of intersection of the selected word line with the selected bit line pair is selected for an access.
The control circuit 20 is used for performing read and write accesses to memory cells. The read and write accesses occur synchronously with the variation of a clock signal CLK which is applied to a clock terminal T. To provide external control of the read and write accesses, a control signal /CS is applied to a control terminal S20a, a control signal /RAS is applied to a control terminal S20b, a control signal /CAS is applied to a control terminal S20c and a control signal /WE is applied to a control terminal S20d of the control circuit 20.
FIG. 2A shows a semiconductor chip HC of a semiconductor memory. Instead of a single memory cell array, the memory cells are arranged here in different memory banks B1, B2, B3 and B4. Between the memory banks, the so-called spine area SP of the semiconductor memory is located. Within the spine area, circuit components such as the control circuit 20 of FIG. 1, register R, voltage generators G and contact pads are arranged. Of possible contact pads, data pads DQ and a monitor pad MP are shown in FIG. 2A. In the later production process of the semiconductor memory, the data pads DQ are connected via bonding wires to the chip pins which are externally accessible. At the monitor pad MP, test signals are provided for testing the semiconductor memory at wafer level.
FIG. 2B shows a single memory bank B which is subdivided into different memory segments (Seg1, Seg2, etc.). At the edge of each segment, a strip SAS, in which the sense amplifiers are arranged, is in each case located.
FIG. 2C shows an enlarged view of the memory segments Seg1 and Seg2, at the edges of which the sense amplifiers SA are arranged in strips. One sense amplifier is in each case connected to one bit line pair BLP. On a bit line pair, the memory cells are in each case arranged at points of intersection of the true and complement bit lines with the word lines WL.
FIG. 3 shows a sense amplifier SA which is constructed as so-called shared sense amplifier. These are sense amplifiers which are arranged between the memory segment Seg1 and the memory segment Seg2 in FIG. 2C. This type of sense amplifier amplifies both cell signals from the segment Seg1 and cell signals of memory cells from the segment Seg2. The true bit line BLT1 and the complement bit line BLC1 lead into the memory segment Seg1, whereas the true bit line BLT2 and the complement bit line BLC2 led into the memory segment Seg2.
To feed an equalizing voltage VEQ into the bit lines of a bit line pair, the controllable switching unit SE is activated. As a result, both bit lines of a bit line pair are charged up to the common equalizing voltage VEQ. To evaluate the cell signal of memory cells in the segment Seg1, the isolation transistors 11 and 12 are activated via a control signal LS so that the bit line pair leading into the segment Seg1 is connected to the sense amplifier SA. To evaluate a cell signal of a memory cell from the memory segment Seg2, the isolation transistors 11′ and 12′ are controlled to conduct by a control signal RS, whereas the isolation transistors 11 and 12 are operated not to conduct. In this case, the true bit line BLT2 and the complement bit line BLC2 are connected with low impedance to the sense amplifier SA.
The transistor pairs 13a, 13b and 14a, 14b with feedback form a monostable flip-flop. The switching transistors 13a and 13b in the form of n-FETs and the switching transistors 14a and 14b in the form of p-type FETs are used for evaluating and amplifying voltage levels on the connected bit lines.
For writing memory information into a memory cell or, respectively, reading memory information from a memory cell, the switching transistors 16a and 16b are controlled to conduct by a write signal WR or a read signal RD. As a result, the sense amplifier is connected to local data lines DL.
In the text which follows, a read access to a memory cell connected to the true bit line BLT is described. According to FIG. 4A, various control signals ACT, WR, RD and PRE, together with address signals X and Y, are applied to the integrated semiconductor memory device synchronously in time with the variation of a clock signal CLK. During the period tRCD, memory cells are activated which are arranged along a word line. A memory arranged along the word line is write-accessed during the period tWR or, respectively, read-accessed during the period tRD. During the period tRP, the bit lines of a bit line pair are precharged to the equalizing voltage VEQ.
FIG. 4B shows a potential variation on a true bit line BLT and a complement bit line BLC of a bit line pair during the reading out of a logic “1” information item.
FIG. 4C shows the variation of a control signal EQS for activating the switching unit for feeding the equalizing voltage VEQ during the precharging of a bit line pair, the variation of a control voltage WLP on a word line, the variation of a control signal nset which is used for controlling the switching transistor 17a, and the variation of a control signal pset which is used for controlling the switching transistor 17b. 
To carry out a read access, the control signal ACT, together with an address signal X, is applied to the integrated semiconductor memory device. The control circuit 20 then evaluates the address signal X and activates the memory cells along the word line defined by the address X. In the subsequent clock period, no control signal is applied to the integrated semiconductor memory device. After that, a read command RD is applied to the control terminals of the control circuit 20. According to the address signal Y, a bit line pair is now selected for the read access within the memory cell array. The memory cell which is connected to the selected word line and to the selected bit line feeds the charge stored in its storage capacitor SC onto the bit line.
If a High level is stored in the memory cell, a slight rise in potential will occur at time t1 on the bit line connected to the memory cell. The potential swing is slightly above the equalizing voltage VEQ to which the bit line pair is charged up. At time t2, the switching transistor 17a is controlled to conduct by the falling edge of the control signal nset. The low voltage potential VBL is thus fed onto the complement bit line BLC via the switching transistor 13a. At time t3, a rising edge of the control signal pset activates the switching transistor 17b. The high voltage level VBH is thus fed onto the true bit line BLT.
When the read time tRD has ended, the control circuit 20 is driven with a precharge command PRE in conjunction with an address signal X. The control circuit 20 then generates a rising edge of the control signal nset and a falling edge of the control signal pset. As a result, the switching transistors 17a and 17b are switched off. The selection transistors along the selected word line are switched off by the low level of the word line voltage WLP. The controllable switching unit SE for feeding the equalizing voltage onto the bit lines of a bit line pair is activated by the rising edge of the control signal EQS. As a result, the bit lines of a bit line pair are connected to one another with low impedance via the controllable switching unit SE. The feeding-in of the equalizing voltage VEQ leads to a potential equalization of the true bit lines BLT and the complement bit line BLC of each bit line pair to the equalizing voltage VEQ.
To carry out a write access, a write command WR is applied to the control circuit instead of the read command RD. Otherwise, the order of the control signals is identical for read and write access.
In the production process, the integrated semiconductor memory device is generally tested at wafer and chip level. A distinction is made between tests which, for example, check the interface timing, read-out problems, short circuits and interrupted connections in the package, data bus couplings and electrical couplings in the case of a DRAM semiconductor memory. To carry out a function test, information is in each case stored in a defined manner along a bit line pair in the memory cells. To examine, for example, the stability of a stored information item, secondary accesses of memory cells connected to an adjacent bit line pair are carried out. Following that, a pass/fail evaluation takes place in that the memory cells which have been influenced by the disturbance are read out again. In the case of a faulty read-out of memory cells, however, it is generally difficult to determine whether the cell quality per se, the read-out transistor, the connected bit line, or for example, the sense amplifier is defective. Similarly, the cause of a fault can lie in insufficiently finely adjusted read-out timing since, for example, the times between controlling a selection transistor to conduct and applying the control signal nset and pset are too close to one another in time. Furthermore, it is currently not possible to vary the read-out timing shown in FIG. 4B in a selective manner by varying, for example, the time interval between the control signals nset and pset.